Quick Addition of Decimals Using Reversible Conservative Logic

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. This research proposes quick addition of decimals (QAD) suitable for multi-digit BCD addition, using reversible conservative logic. The design makes use of reversible fault tolerant Fredkin gates only. The implementation strategy is to reduce the number of levels of delay there by increasing the speed, which is the most important factor for high speed circuits.

Ethernet Telemetry for Towed Arrays

The towed array electronics is essentially a multichannel real time data acquisition system. The major challenges involved in it are the simultaneous acquisition of data from multiple channels, telemetry of the data over tow cable (several kilometres in some systems) and synchronization with the onboard receiver for accurate reconstruction. A serial protocol is best suited to transmit the data to onboard electronics since number of wires inside the tow cable is limited. The best transmission medium for data over large distances is the optical fibre. In this a two step approach towards the realization of a reliable telemetry scheme for the sensor data using standard protocols is described. The two schemes are discussed in this paper. The first scheme is for conversion of parallel, time-multiplexed multi-sensor data to Ethernet. Existing towed arrays can be upgraded to ethernet using this scheme. Here the last lap of the transmission is by Ethernet over Fibre. For the next generation of towed arrays it is required to digitize and convert the data to ethernet close to the sensor. This is the second scheme. At the heart of this design is the Analog-to-Ethernet node. In addition to a more reliable interface, this helps in easier fault detection and firmware updates in the field for the towed arrays. The design challenges and considerations for incorporating a network of embedded devices within the array are highlighted

Fault Tolerant Error Coding and Detection using Reversible Gates

In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction – double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4 x 4 reversible gate called ‘HCG’ for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits.